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V62C2802048L(L)
Ultra Low Power 256K x 8 CMOS SRAM
Features
* Low-power consumption - Active: 35mA at 55ns - Stand-by: 10 A (CMOS input/output) 2 A CMOS input/output, L version * Single +2.2 to 2.7V Power Supply_Typical * Extented Voltage from 2.2 to 3.6V. * Equal access and cycle time * 55/70/85/100 ns access time * Easy memory expansion with CE1, CE2 and OE inputs * 1.0V data retention mode * TTL compatible, Tri-state input/output * Automatic power-down when deselected * Package available: 32L TSOP(I)/ STSOP(I) * 48 Ball CSP_BGA
Functional Description
The V62C2802048L is a low power CMOS Static RAM organized as 262,144 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, an active HIGH CE2, an active LOW OE, and Tri-state I/O's. This device has an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking Chip Enable 1 (CE1) with Write Enable (WE) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1) with Output Enable (OE) LOW while Write Enable (WE) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. TheV62C2802048LL comes with a 1V data retention feature and Lower Standby Power. The V62C2802048L is avalable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm and CSP type 48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP (CSP_BGA See next page)
A11 A9 A8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
INPUT BUFFER
ROW DECODER
SENSE AMP
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A13 WE CE2
I/O8
A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4
Cell Array
I/O1
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16 A17
CONTROL CIRCUIT
OE WE CE1 CE2
1 REV. 1.2 May 2001 V62C2802048L(L)
V62C2802048L(L)
MOSEL VITELIC
1 2 3 4
V62C2802048L(L)B
5 6 1 2 3 4 5 6
A B
A0
A1
CS2
A3
A6
A8
I/O5
A2
WE
A4
A7
I/O1
C
I/O6
NC
NC
A5
NC
I/O2
D E
VSS
NC
NC
NC
NC
VCC
VCC
NC
NC
NC
NC
VSS
F G H
I/O7
NC
NC
A17
NC
I/O3
I/O8 A9
OE A10
CS1 A11
A16 A12
A15 A13
I/O4 A14
Note: NC means no Ball.
Top View
Top View
48 Ball - 9x12 fpBGA (Ultra Low Power)
C A1
PACKAGE OUTLINE DWG.
SYMBOL A
UNIT:MM 1.05+0.15 0.25+0.05 0.35+.05 0.30(TYP) 12.00+0.10 5.25 9.00+0.10 3.75 0.75TYP 0.10
A
aaa
SIDE VIEW
A1 b c
D D1
D D1 E
6
e
E1 e
5
aaa
E1
4
3
2
1 A B C D E F G H
BOTTOM VIEW
b SOLDER BALL
2
REV. 1.2 May 2001 V62C2802048L(L)
E
V62C2802048L(L)
Absolute Maximum Ratings * Parameter
Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature (Plastic) Temperature Under Bias
Symbol
Vt PT Tstg Tbias
Minimum
-0.5 - -55 -40
Maximum
3.6 1.0 +150 +85
Unit
V W
0C 0
C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table CE1
H X L L L
CE2
X L H H H
WE
X X H H L
OE
X X L H X
Data
High-Z High-Z Data Out High-Z Data In Standby Standby Active, Read
Mode
Active, Output Disable Active, Write
* Key: X = Don't Care, L = Low, H = High
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter
Supply Voltage
Symbol
VCC Gnd VIH VIL
Min
2.2 0.0 2.0 -0.5*
Typ
2.5 0.0 -
Max
2.7 0.0 VCC + 0.2 0.6
Unit
V V V V
Input Voltage
* VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature
3
REV. 1.2 May 2001 V62C2802048L(L)
V62C2802048L(L)
DC Operating Characteristics (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter
Input Leakage Current Output Leakage Current Operating Power Supply Current Average Operating Current
Sym
Test Conditions
Vcc = Max, Vin = Gnd to Vcc CE1 = VIH or CE2 = VIL Vcc= Max, VOUT = Gnd to Vcc CE1 = VIL , CE2 = VIH VIN = VIH or VIL , IOUT = 0 mA CE1 = VIL , CE2 = VIH IOUT = 0mA, Min Cycle, 100% Duty CE1 = 0.2V, CE2 = Vcc - 0.2V IOUT = 0mA,
-55
1 1 3 35 -
-70
1 1 3 30 -
-85
1 1 3 25 -
-100
1 1 3 20
Min Max Min Max Min Max Min Max
Unit
A A mA
IILII IILOI
ICC ICC1
mA
ICC2
-
3
-
3
-
3
-
3
mA
Cycle Time=1s, 100% Duty
Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage Output High Voltage
ISB ISB1
CE1 = VIH or CE2 = VIL CE1 > Vcc - 0.2V or CE2 < 0.2V, f = 0 VIN < 0.2V or VIN > Vcc- 0.2V IOL = 2 mA IOH = -2 mA
-
0.5 10 2 0.4 -
2.0
0.5 10 2 0.4 -
2.0
0.5 10 2 0.4 -
2.0
0.5 10 2 0.4 -
mA A A V V
L
2.0
VOL VOH
Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol
Input Capacitance I/O Capacitance
Test Condition
Vin = 0V Vin = Vout = 0V
Max
7 8
Unit
pF pF
Cin CI/O
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level 0.6V to 2.2V 5ns
TTL
Input Rise and Fall Time Input and Output Timing Reference Level
CL*
1.4V
Output Load Condition
70ns/85 ns C
L
Figure A.
* Including Scope and Jig Capacitance
= 30pf + 1TTL Load
Load 100ns/120 ns
CL= 100pf + 1TTL Load
4
REV. 1.2 May 2001 V62C2802048L(L)
V62C2802048L(L)
Read Cycle (3,9) (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z Power-Up Time Power-Down Time
Symbol
tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD 55 10 10 5 0 -
-55
55 55 35 25 25 55 70 10 10 5 0 -
-70
70 70 40 30 25 70 85 10 10 5 0 -
-85
85 85 40 35 30 85
-100
100 10 10 5 0 100 100 50 40 35 100
Unit
ns ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max Min Max
4,5 4,5 4,5 4,5 5 5
Write Cycle (3,11) (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter
Write Cycle Time Chip Enable to Write End Address Setup to Write End Address Setup Time Write Pulse Width Write Recovering Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End
Symbol
tWC tCW tAW tAS tWP tWR tDW tDH tWZ tOW 55 45 45 0 45 0 25 0 5
-55
-70
-85
-100
Unit
ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max Min Max
25 70 60 60 0 50 0 30 0 5 30 85 70 70 0 60 0 35 0 5 35 100 80 80 0 70 0 40 0 5
40 -
4,5 4,5
5
REV. 1.2 May 2001 V62C2802048L(L)
V62C2802048L(L)
Timing Waveform of Read Cycle 1(Address Controlled) (3,6,7,9)
t RC Address tAA DOUT tOH Data Valid
Timing Waveform of Read Cycle 2(CE1 Controlled)(5,6,8,9)
tRC CE1 tOE tOLZ tACE DOUT tCLZ
Supply Current
OE
tOHZ tCHZ Data Valid tPD ICC
50% 50%
tPU
ISB
Timing Waveform of Read Cycle 3(CE2 Controlled) (3,6,8,9)
tRC CE2 OE tOLZ tACE DOUT tCLZ
Supply Current
tOE tOHZ tCHZ Data Valid tPD ICC
50% 50%
tPU
ISB
6
REV. 1.2 May 2001 V62C2802048L(L)
V62C2802048L(L)
Timing Waveform of Write Cycle 1
(WE Controlled)(10,11)
tAW tWC tWR
Address WE tAS DIN tWZ DOUT tWP tDW Data Valid tOW tDH
Timing Waveform of Write Cycle 2
tAW Address tAS CE1 WE tWZ DIN DOUT tCW
(CE1 Controlled) (10,11)
tWC tWR
tWP tDW tDH
Data Valid
Timing Waveform of Write Cycle 3
tAW Address tAS CE2 tCW
(CE2 Controlled) (10,11)
tWC tWR
tWP WE tWZ DIN DOUT tDW tDH
Data Valid
REV. 1.2 May 2001 V62C2802048L(L)
7
V62C2802048L(L)
Data Retention Characteristics (L Version Only)(1) Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time(2)
Symbol
VDR ICCDR tCDR tR
Test Condition
CE1 > VCC - 0.2V or CE2 < + 0.2V VIN > VCC - 0.2V or VIN < 0.2V
Min
1.0 0 tRC
Max
-
Unit
V A ns ns
1 -
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
Data Retention Mode
VCC
Vcc Typ VDR > 1.0V Vcc Typ
tCDR CE
VDR
tR
VIH
VIH
Notes
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. All read cycle timings are referenced from the last valid address to the first transtion address. CE1 or WE must be HIGH or CE2 must be LOW during address transition. All write cycle timings are referenced from the last valid address to the first transition address.
8
REV. 1.2 May 2001 V62C2802048L(L)
V62C2802048L(L)
Ordering Information
Device Type* V62C2802048L-55T V62C2802048L-70T V62C2802048L-85T V62C2802048L-100T V62C2802048LL-55T V62C2802048LL-70T V62C2802048LL-85T V62C2802048LL-100T V62C2802048L(L)-55V V62C2802048L(L)-70V V62C2802048L(L)-85V V62C2802048L(L)-100V V62C2802048L(L)-55B V62C2802048L(L)-70B V62C2802048L(L)-85B V62C2802048L(L)-100B Speed 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 8 x 13.4 mm 32-pin Plastic STSOP Package 8 x 20 mm 32-pin Plastic TSOP1
48-fpBGA
* For Industrial Temperature tested devices, an "I" designator will be added to the end of the Device number.
9
REV. 1.2 May 2001 V62C2802048L(L)
MOSEL VITELIC
U.S.A.
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V62C2802048L(L)
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U.S. SALES OFFICES
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(c) Copyright 2001, MOSEL VITELIC Inc.
5/01 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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